module mv24clk(clock, resetn, in, out);

input			clock, resetn;
input			in;
output			out;

reg				out;

wire			full;
wire	[4:0]	q;
wire	[4:0]	ref;

assign			ref = 5'b01100;

reg				cnten_mvcnt, sclr_mvcnt;

parameter		IDLE=0, CNT=1;
reg				STATE;

lpm_mvcnt		lpm_mvcnt_inst (.clock(clock), .cnt_en(cnten_mvcnt), .sclr(sclr_mvcnt),
								.aclr(~resetn), .q(q));
lpm_mvcomp		lpm_mvcomp_inst (.dataa(q), .datab(ref), .ageb(full));

always @(posedge clock or negedge resetn)
begin: NEXT_CURR
if (!resetn)
	STATE <= IDLE;
else
	case (STATE)
		IDLE:
			if (in) STATE <= CNT;
			else STATE <= IDLE;
		CNT:
			if (full) STATE <= IDLE;
			else STATE <= CNT;
		default: STATE <= IDLE;
	endcase
end

always @(STATE)
begin: STATE_DECODING
case (STATE)
	IDLE:
		begin
			cnten_mvcnt <= 0;
			sclr_mvcnt <= 1;
			out <= 0;
		end
	CNT:
		begin
			cnten_mvcnt <= 1;
			sclr_mvcnt <= 0;
			out <= 1;
		end
	default:
		begin
			cnten_mvcnt <= 0;
			sclr_mvcnt <= 1;
			out <= 0;
		end		
endcase
end
endmodule